Work with David Brooks | NotedSource
David Brooks is the Haley Family Professor of Computer
Science in the School of Engineering and Applied Sciences
at Harvard University. His research interests include
hardware and software design for computer systems, with an
emphasis on energy-efficient computer architectures for
high-performance and embedded systems. Several innovations
from his research including dynamic thermal management,
integrated voltage regulators, and AI hardware/software
co-design have been adopted in commercial systems. Prof.
Brooks received his Ph.D. from Princeton University in
2001 and his Bachelors from the University of Southern
California in 1997. He has been a Professor at Harvard
since 2002 and was a Research Staff Member at IBM from
2001 to 2002. He has previously visited Facebook/Meta for
sabbaticals as a research scientist. Prof. Brooks is a
Fellow of the ACM and IEEE and has received several honors
and awards including the ACM Maurice Wilkes Award, two
HPCA Test of Time Awards, and the ISCA Influential Paper
Award.
https://cv.notedsource.io/me/1PJKD3WR
David Brooks
Haley Family Professor of Computer Science, Harvard University
Cambridge, Massachusetts, United States
of America
Research Expertise
Computer Architecture
Power and Energy Efficient Computing
AI Hardware/Software Codesign
About
David Brooks is the Haley Family Professor of
Computer Science in the School of Engineering
and Applied Sciences at Harvard University.
His research interests include hardware and
software design for computer systems, with an
emphasis on energy-efficient computer
architectures for high-performance and
embedded systems. Several innovations from his
research including dynamic thermal management,
integrated voltage regulators, and AI
hardware/software co-design have been adopted
in commercial systems. Prof. Brooks received
his Ph.D. from Princeton University in 2001
and his Bachelors from the University of
Southern California in 1997. He has been a
Professor at Harvard since 2002 and was a
Research Staff Member at IBM from 2001 to
2002. He has previously visited Facebook/Meta
for sabbaticals as a research scientist. Prof.
Brooks is a Fellow of the ACM and IEEE and has
received several honors and awards including
the ACM Maurice Wilkes Award, two HPCA Test of
Time Awards, and the ISCA Influential Paper
Award.
Publications
Wattch
ACM SIGARCH Computer Architecture
News
2000
Dynamic thermal management for
high-performance microprocessors
Proceedings HPCA Seventh International
Symposium on High-Performance Computer
Architecture
System level analysis of fast, per-core
DVFS using on-chip switching regulators
2008 IEEE 14th International Symposium
on High Performance Computer
Architecture
2008
Applied Machine Learning at Facebook: A
Datacenter Infrastructure Perspective
2018 IEEE International Symposium on
High Performance Computer Architecture
(HPCA)
2018
Minerva
ACM SIGARCH Computer Architecture
News
2016
Accurate and efficient regression modeling
for microarchitectural performance and
power prediction
ACM SIGOPS Operating Systems
Review
2006
Power-aware microarchitecture: design and
modeling challenges for next-generation
microprocessors
IEEE Micro
2000
Profiling a warehouse-scale computer
Proceedings of the 42nd Annual
International Symposium on Computer
Architecture
2015
Machine Learning at Facebook:
Understanding Inference at the Edge
2019 IEEE International Symposium on
High Performance Computer Architecture
(HPCA)
2019
Bioinformatics Research Challenges and
Opportunities in Machine Learning
2022 International Conference on
Augmented Intelligence and Sustainable
Systems (ICAISS)
2022
Dynamically exploiting narrow width
operands to improve processor power and
performance
Proceedings Fifth International
Symposium on High-Performance Computer
Architecture
1999
Aladdin
ACM SIGARCH Computer Architecture
News
2014
A conceptual peer review model for arXiv
and other preprint databases
Learned Publishing
2019
Ares
Proceedings of the 55th Annual Design
Automation Conference
2018
Thread motion
ACM SIGARCH Computer Architecture
News
2009
MLPerf: An Industry Standard Benchmark
Suite for Machine Learning Performance
IEEE Micro
2020
MachSuite: Benchmarks for accelerator
design and customized architectures
2014 IEEE International Symposium on
Workload Characterization (IISWC)
2014
Chasing Carbon: The Elusive Environmental
Footprint of Computing
2021 IEEE International Symposium on
High-Performance Computer Architecture
(HPCA)
2021
The Architectural Implications of
Facebook's DNN-Based Personalized
Recommendation
2020 IEEE International Symposium on
High Performance Computer Architecture
(HPCA)
2020
A Fully-Integrated 3-Level DC-DC Converter
for Nanosecond-Scale DVFS
IEEE Journal of Solid-State
Circuits
2012
A Dynamic Compilation Framework for
Controlling Microprocessor Energy and
Performance
38th Annual IEEE/ACM International
Symposium on Microarchitecture
(MICRO'05)
Methods of inference and learning for
performance modeling of parallel
applications
Proceedings of the 12th ACM SIGPLAN
symposium on Principles and practice of
parallel programming
2007
Understanding Voltage Variations in Chip
Multiprocessors using a Distributed
Power-Delivery Network
2007 Design, Automation & Test in
Europe Conference & Exhibition
2007
RecNMP: Accelerating Personalized
Recommendation with Near-Memory Processing
2020 ACM/IEEE 47th Annual International
Symposium on Computer Architecture
(ISCA)
2020
An Ultra Low Power System Architecture for
Sensor Network Applications
32nd International Symposium on
Computer Architecture (ISCA'05)
Co-designing accelerators and SoC
interfaces using gem5-Aladdin
2016 49th Annual IEEE/ACM International
Symposium on Microarchitecture
(MICRO)
2016
DeepRecSys: A System for Optimizing
End-To-End At-Scale Neural Recommendation
Inference
2020 ACM/IEEE 47th Annual International
Symposium on Computer Architecture
(ISCA)
2020
14.3 A 28nm SoC with a 1.2GHz
568nJ/prediction sparse
deep-neural-network engine with >0.1
timing error rate tolerance for IoT
applications
2017 IEEE International Solid-State
Circuits Conference (ISSCC)
2017
Fathom: reference workloads for modern
deep learning methods
2016 IEEE International Symposium on
Workload Characterization (IISWC)
2016
Performance, Energy, and Thermal
Considerations for SMT and CMP
Architectures
11th International Symposium on
High-Performance Computer
Architecture
Control techniques to eliminate voltage
emergencies in high performance processors
The Ninth International Symposium on
High-Performance Computer Architecture,
2003. HPCA-9 2003. Proceedings.
CMP Design Space Exploration Subject to
Physical Constraints
The Twelfth International Symposium on
High-Performance Computer Architecture,
2006.
Cheetah: Optimizing and Accelerating
Homomorphic Encryption for Private
Inference
2021 IEEE International Symposium on
High-Performance Computer Architecture
(HPCA)
2021
Energy characterization and
instruction-level energy model of Intel's
Xeon Phi processor
International Symposium on Low Power
Electronics and Design (ISLPED)
2013
Optimizing pipelines for power and
performance
35th Annual IEEE/ACM International
Symposium on Microarchitecture, 2002.
(MICRO-35). Proceedings.
Power, Thermal, and Reliability Modeling
in Nanometer-Scale Microprocessors
IEEE Micro
2007
Illustrative Design Space Studies with
Microarchitectural Regression Models
2007 IEEE 13th International Symposium
on High Performance Computer
Architecture
2007
Mitigating the Impact of Process
Variations on Processor Register Files and
Execution Units
2006 39th Annual IEEE/ACM International
Symposium on Microarchitecture
(MICRO'06)
2006
New methodology for early-stage,
microarchitecture-level power-performance
analysis of microprocessors
IBM Journal of Research and
Development
2003
Survey of Hardware Systems for Wireless
Sensor Networks
Journal of Low Power Electronics
2008
An Adaptive Issue Queue for Reduced Power
at High Performance
Lecture Notes in Computer Science
2001
Quantifying sources of error in McPAT and
potential impacts on architectural studies
2015 IEEE 21st International Symposium
on High Performance Computer
Architecture (HPCA)
2015
Voltage emergency prediction: Using
signatures to reduce operating margins
2009 IEEE 15th International Symposium
on High Performance Computer
Architecture
2009
ACT
Proceedings of the 49th Annual
International Symposium on Computer
Architecture
2022
A fully-integrated 3-level DC/DC converter
for nanosecond-scale DVS with fast shunt
regulation
2011 IEEE International Solid-State
Circuits Conference
2011
Process Variation Tolerant 3T1D-Based
Cache Architectures
40th Annual IEEE/ACM International
Symposium on Microarchitecture (MICRO
2007)
2007
EdgeBERT: Sentence-Level Energy
Optimizations for Latency-Aware Multi-Task
NLP Inference
MICRO-54: 54th Annual IEEE/ACM
International Symposium on
Microarchitecture
2021
Voltage Smoothing: Characterizing and
Mitigating Voltage Noise in Production
Processors via Software-Guided Thread
Scheduling
2010 43rd Annual IEEE/ACM International
Symposium on Microarchitecture
2010
HELIX
Proceedings of the Tenth International
Symposium on Code Generation and
Optimization
2012
Carbon Explorer: A Holistic Framework for
Designing Carbon Aware Datacenters
Proceedings of the 28th ACM
International Conference on
Architectural Support for Programming
Languages and Operating Systems, Volume
2
2023
RecSSD: near data processing for solid
state drive based recommendation inference
Proceedings of the 26th ACM
International Conference on
Architectural Support for Programming
Languages and Operating Systems
2021
CPR: Composable performance regression for
scalable multiprocessor models
2008 41st IEEE/ACM International
Symposium on Microarchitecture
2008
A circuit level implementation of an
adaptive issue queue for power-aware
microprocessors
Proceedings of the 11th Great Lakes
symposium on VLSI
2001
DeCoR: A Delayed Commit and Rollback
mechanism for handling inductive noise in
processors
2008 IEEE 14th International Symposium
on High Performance Computer
Architecture
2008
Value-based clock gating and operation
packing
ACM Transactions on Computer
Systems
2000
A case for efficient accelerator design
space exploration via Bayesian
optimization
2017 IEEE/ACM International Symposium
on Low Power Electronics and Design
(ISLPED)
2017
DNN Engine: A 28-nm Timing-Error Tolerant
Sparse Deep Neural Network Processor for
IoT Applications
IEEE Journal of Solid-State
Circuits
2018
Algorithm-Hardware Co-Design of Adaptive
Floating-Point Encodings for Resilient
Deep Learning Inference
2020 57th ACM/IEEE Design Automation
Conference (DAC)
2020
Tradeoffs between power management and
tail latency in warehouse-scale
applications
2014 IEEE International Symposium on
Workload Characterization (IISWC)
2014
ISA-independent workload characterization
and its implications for specialized
architectures
2013 IEEE International Symposium on
Performance Analysis of Systems and
Software (ISPASS)
2013
The accelerator store
ACM Transactions on Architecture and
Code Optimization
2012
Tribeca
Proceedings of the 42nd Annual IEEE/ACM
International Symposium on
Microarchitecture
2009
ReVIVaL
ACM SIGARCH Computer Architecture
News
2008
Integrated analysis of power and
performance for pipelined microprocessors
IEEE Transactions on Computers
2004
HELIX-RC
ACM SIGARCH Computer Architecture
News
2014
Efficiency trends and limits from
comprehensive microarchitectural
adaptivity
ACM SIGARCH Computer Architecture
News
2008
Gradient-Leakage Resilient Federated
Learning
2021 IEEE 41st International Conference
on Distributed Computing Systems
(ICDCS)
2021
Towards a software approach to mitigate
voltage emergencies
Proceedings of the 2007 international
symposium on Low power electronics and
design
2007
Logic Compatible High-Performance
Ferroelectric Transistor Memory
IEEE Electron Device Letters
2022
MASR: A Modular Accelerator for Sparse
RNNs
2019 28th International Conference on
Parallel Architectures and Compilation
Techniques (PACT)
2019
Understanding the energy efficiency of
simultaneous multithreading
Proceedings of the 2004 international
symposium on Low power electronics and
design
2004
Early-Stage Definition of LPX: A Low Power
Issue-Execute Processor
Lecture Notes in Computer Science
2003
SMAUG
ACM Transactions on Architecture and
Code Optimization
2020
HELIX-UP: Relaxing program semantics to
unleash parallelization
2015 IEEE/ACM International Symposium
on Code Generation and Optimization
(CGO)
2015
Dimetrodon
Proceedings of the 48th Design
Automation Conference
2011
The Aladdin Approach to Accelerator Design
and Modeling
IEEE Micro
2015
Eliminating voltage emergencies via
microarchitectural voltage control
feedback and dynamic optimization
Proceedings of the 2004 international
symposium on Low power electronics and
design
2004
Mask synthesis using machine learning
software and hardware platforms
Optical Microlithography XXXIII
2020
On-Chip Deep Neural Network Storage with
Multi-Level eNVM
2018 55th ACM/ESDA/IEEE Design
Automation Conference (DAC)
2018
Mallacc
ACM SIGPLAN Notices
2017
Architectural power models for sram and
cam structures based on hybrid
analytical/empirical techniques
2007 IEEE/ACM International Conference
on Computer-Aided Design
2007
An accelerator-based wireless sensor
network processor in 130nm CMOS
Proceedings of the 2009 international
conference on Compilers, architecture,
and synthesis for embedded systems
2009
An event-guided approach to reducing
voltage noise in processors
2009 Design, Automation & Test in
Europe Conference & Exhibition
2009
Replacing 6T SRAMs with 3T1D DRAMs in the
L1 Data Cache to Combat Process
Variability
IEEE Micro
2008
A new blind separation method for
under-determined speech signals based on
single source interval pre-extraction
MATEC Web of Conferences
2021
Can Subthreshold and Near-Threshold
Circuits Go Mainstream?
IEEE Micro
2010
A Fully Integrated Reconfigurable
Switched-Capacitor DC-DC Converter With
Four Stacked Output Channels for Voltage
Stacking Applications
IEEE Journal of Solid-State
Circuits
2016
Revival: A Variation-Tolerant Architecture
Using Voltage Interpolation and Variable
Latency
IEEE Micro
2009
Power-Performance Modeling and Tradeoff
Analysis for a High End Microprocessor
Lecture Notes in Computer Science
2001
Deep Learning for Computer Architects
Synthesis Lectures on Computer
Architecture
2017
Run-time power estimation in high
performance microprocessors
Proceedings of the 2001 international
symposium on Low power electronics and
design - ISLPED '01
2001
Characterizing and evaluating voltage
noise in multi-core near-threshold
processors
International Symposium on Low Power
Electronics and Design (ISLPED)
2013
TinyBench: the case for a standardized
benchmark suite for TinyOS based wireless
sensor network devices
29th Annual IEEE International
Conference on Local Computer
Networks
Neural Implementation of Bayesian
Inference in Population Codes
Advances in Neural Information
Processing Systems 14
2002
Research Infrastructures for Hardware
Accelerators
Synthesis Lectures on Computer
Architecture
2015
Dynamic-Compiler-Driven Control for
Microprocessor Energy and Performance
IEEE Micro
2006
Automatic Domain-Specific SoC Design for
Autonomous Unmanned Aerial Vehicles
2022 55th IEEE/ACM International
Symposium on Microarchitecture
(MICRO)
2022
MaxNVM
Proceedings of the 52nd Annual IEEE/ACM
International Symposium on
Microarchitecture
2019
Achieving uniform performance and
maximizing throughput in the presence of
heterogeneity
2011 IEEE 17th International Symposium
on High Performance Computer
Architecture
2011
Education
Princeton University
Ph.D., Electrical Engineering / 2001
Princeton, New Jersey, United
States of America
Experience
Harvard University
Meta
Links & Social Media
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