Rogério Paludo, PhD

Senior Staff Security Verification | Hardware Security, Applied Cryptography & Side-Channel Analysis

About

I am a Senior Staff Security Verification Engineer with a PhD in Electrical Engineering, currently working on secure hardware at Infineon Technologies. My expertise spans pre-silicon digital design and formal verification, with a specialized focus on cryptographic architectures and post-quantum cryptography (PQC). My academic research has heavily focused on privacy-preserving cloud computing, specifically architecting high-performance hardware accelerators for Fully Homomorphic Encryption (FHE).

Education

Instituto Superior Técnico

Postdoctoral Researcher, Electrical and Electronics Engineering / December, 2022

Universidade Federal de Santa Catarina

Doctorate, Electrical and Electronics Engineering / December, 2020

Universidade Federal de Santa Catarina

Master's degree, Electrical and Electronics Engineering / December, 2016

Universidade Estadual do Oeste do Paraná

Bachelor's degree, Electrical Engineering - Control Systems / December, 2013

Experience

Infineon Technologies

Senior Staff Security Verification / May, 2025Present

Technology Innovation Institute

Lead Hardware Engineer / January, 2023February, 2025

◦ Research: Designing FPGA accelerators for privacy-preserving machine learning taking advantage of maximum PCIe and HBM2.0 bandwidth. Responsible for architecture, implementation, verification, validation, and, integration of the accelerators into the software stack. ◦ Development: Working at the national security level developing cryptographic hardware for i) asymmetric cryptography (ECDSA & ECDH); ii) symmetric cryptography (FIPS202–SHA3); iii) post-quantum cryptography (PQC). Complete ownership of high-assurance PQC key-encapsulation (FIPS203) and digital signatures (FIPS204) implementations - from architecture specifications, formal verification, and validation over the board.

Crypto Quantique

Digital ASIC/FPGA engineer / August, 2022December, 2022

Worked on quantum PUF technology mostly on digital design and BCH codes implementations.

Astrolight

Consulting Specialist / July, 2022September, 2022

Early stage work on SDR simulations targeting a Testbed for Disruption Tolerant Low Earth Orbit Data Relay System in partnership with ESA.

Capgemini Engineering

Advanced Consultant Engineer / February, 2022August, 2022

Worked on physical realization of QKD.

INESC-ID

Postdoctoral Researcher / April, 2020February, 2022

Worked on several things: - Software Future-TPM (https://futuretpm.eu/) - Lattice-based Direct Anonymous Attestation (https://cordis.europa.eu/project/id/779391/reporting) - Fully-homomorphic encryption, RISC-V, on hardware (FPGAs and ASICs), and software + compilers (https://github.com/rogpld/fhentt)

Universidade Federal de Santa Catarina

PHD Candidate / March, 2016April, 2020

◦ PhD Thesis: Developed efficient arithmetic circuits using alternative forms of numeric representation for high-performance digital signal processing and cryptography systems. Implemented a framework for design automation of the specialized arithmetic circuits targeting applications in digital signal processing and cryptography.

Masters Candidate / January, 2014March, 2016

◦ Master Thesis: Developed a framework for early semi-formal verification of mission-critical embedded software in the Master Thesis. Used the https://floripasat.ufsc.br/ as a study case. Participated in a R&D project with Freescale Semiconductors for the design of a mixed-signal verification library used in the tapeout of a power-management IP.

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