Vijay Janapa Reddi

Harvard University

Research Expertise

Computer Architecture
Machine Learning Systems
Autonomous Agents

About

Dr. Vijay Janapa Reddi is an Associate Professor of Engineering and Applied Sciences at Harvard University, where his research focuses on the intersection of computer architecture, machine learning systems, and autonomous agents. His multidisciplinary expertise drives advancements in efficient and intelligent computing systems across scales, from mobile and edge platforms to Internet of Things (IoT) devices. Prior to joining Harvard, Dr. Janapa Reddi was an Associate Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. In addition to his academic role, Dr. Janapa Reddi is deeply involved in shaping the future of machine learning and edge AI technologies. He serves as Vice President and co-founder of MLCommons, a nonprofit organization dedicated to accelerating machine learning innovation. In this capacity, he oversees the MLCommons Research organization, sits on its board of directors, and co-led the development of the MLPerf benchmarks, which evaluates a wide range of ML systems from megawatt to microwatt scales. Dr. Janapa Reddi also serves on the boards of directors for the EDGE AI Foundation, fostering academic-industry partnerships at the edge of AI. Throughout his career, Dr. Janapa Reddi has earned numerous awards and accolades, including the Gilbreth Lecturer Honor from the National Academy of Engineering (NAE) in 2016, the IEEE TCCA Young Computer Architect Award (2016), the Intel Early Career Award (2013), and Google Faculty Research Awards in 2012, 2013, 2015, 2017, and 2020. He has also received Best Paper awards at the 2020 Design Automation Conference (DAC), the 2005 International Symposium on Microarchitecture (MICRO), and the 2009 International Symposium on High-Performance Computer Architecture (HPCA). Additionally, he has won various honors and awards, including IEEE Top Picks in Computer Architecture (2006, 2010, 2011, 2016, 2017, 2022, 2023). He is included in the MICRO and HPCA Halls of Fame (inducted in 2018 and 2019, respectively). Dr. Janapa Reddi is passionate about expanding access to applied machine learning and promoting diversity in STEM. He has developed an open-source book, "Machine Learning Systems," (mlsysbook.ai) which is widely adopted by institutions worldwide. Additionally, he created the Tiny Machine Learning (TinyML) series on edX, a massive open online course that has trained over 100,000 students globally in recent years. Dr. Janapa Reddi holds a Ph.D. in computer science from Harvard University, an M.S. in electrical and computer engineering from the University of Colorado at Boulder, and a B.S. in computer engineering from Santa Clara University.

Publications

Pin

ACM SIGPLAN Notices / Jun 12, 2005

Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., & Hazelwood, K. (2005). Pin: building customized program analysis tools with dynamic instrumentation. ACM SIGPLAN Notices, 40(6), 190–200. https://doi.org/10.1145/1064978.1065034

GPUWattch

ACM SIGARCH Computer Architecture News / Jun 23, 2013

Leng, J., Hetherington, T., ElTantawy, A., Gilani, S., Kim, N. S., Aamodt, T. M., & Reddi, V. J. (2013). GPUWattch: enabling energy optimizations in GPGPUs. ACM SIGARCH Computer Architecture News, 41(3), 487–498. https://doi.org/10.1145/2508148.2485964

What is TensorFlow Lite

TensorFlow Lite for Mobile Development / Jan 01, 2020

Zaman, F. (2020). What is TensorFlow Lite. In TensorFlow Lite for Mobile Development. Apress. https://doi.org/10.1007/978-1-4842-6666-3_1

The Vision Behind MLPerf: Understanding AI Inference Performance

IEEE Micro / May 01, 2021

Reddi, V. J., Cheng, C., Kanter, D., Mattson, P., Schmuelling, G., & Wu, C.-J. (2021). The Vision Behind MLPerf: Understanding AI Inference Performance. IEEE Micro, 41(3), 10–18. https://doi.org/10.1109/mm.2021.3066343

Deep Reinforcement Learning for Cyber Security

IEEE Transactions on Neural Networks and Learning Systems / Aug 01, 2023

Nguyen, T. T., & Reddi, V. J. (2023). Deep Reinforcement Learning for Cyber Security. IEEE Transactions on Neural Networks and Learning Systems, 34(8), 3779–3795. https://doi.org/10.1109/tnnls.2021.3121870

MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance

IEEE Micro / Mar 01, 2020

Mattson, P., Reddi, V. J., Cheng, C., Coleman, C., Diamos, G., Kanter, D., Micikevicius, P., Patterson, D., Schmuelling, G., Tang, H., Wei, G.-Y., & Wu, C.-J. (2020). MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance. IEEE Micro, 40(2), 8–16. https://doi.org/10.1109/mm.2020.2974843

Adoption of public interventions for adolescent alcohol use in Portugal: challenges and opportunities

IACAPAP ArXiv / Jan 01, 2020

Picoito, J. (2020). Adoption of public interventions for adolescent alcohol use in Portugal: challenges and opportunities. IACAPAP ArXiv. https://doi.org/10.14744/iacapaparxiv.2020.20003

A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)

Qiang Wu, Martonosi, M., Clark, D. W., Reddi, V. J., Connors, D., Youfeng Wu, Jin Lee, & Brooks, D. (n.d.). A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’05), 271–282. https://doi.org/10.1109/micro.2005.7

TinyOL: TinyML with Online-Learning on Microcontrollers

2021 International Joint Conference on Neural Networks (IJCNN) / Jul 18, 2021

Ren, H., Anicic, D., & Runkler, T. A. (2021, July 18). TinyOL: TinyML with Online-Learning on Microcontrollers. 2021 International Joint Conference on Neural Networks (IJCNN). https://doi.org/10.1109/ijcnn52387.2021.9533927

Web search using mobile cores

ACM SIGARCH Computer Architecture News / Jun 19, 2010

Janapa Reddi, V., Lee, B. C., Chilimbi, T., & Vaid, K. (2010). Web search using mobile cores: quantifying and mitigating the price of efficiency. ACM SIGARCH Computer Architecture News, 38(3), 314–325. https://doi.org/10.1145/1816038.1816002

PIN

Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04 / Jan 01, 2004

Reddi, V. J., Settle, A., Connors, D. A., & Cohn, R. S. (2004). PIN: a binary instrumentation tool for computer architecture research and education. Proceedings of the 2004 Workshop on Computer Architecture Education Held in Conjunction with the 31st International Symposium on Computer Architecture - WCAE ’04, 22-es. https://doi.org/10.1145/1275571.1275600

LatinX in AI at Neural Information Processing Systems Conference 2021

Dec 07, 2021

LatinX in AI at Neural Information Processing Systems Conference 2021. (2021, December 7). https://doi.org/10.52591/lxai202112070

PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

IEEE Transactions on Dependable and Secure Computing / Apr 01, 2009

Shye, A., Blomstedt, J., Moseley, T., Reddi, V. J., & Connors, D. A. (2009). PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures. IEEE Transactions on Dependable and Secure Computing, 6(2), 135–148. https://doi.org/10.1109/tdsc.2008.62

High-performance and energy-efficient mobile web browsing on big/little systems

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) / Feb 01, 2013

Yuhao Zhu, & Reddi, V. J. (2013). High-performance and energy-efficient mobile web browsing on big/little systems. 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 13–24. https://doi.org/10.1109/hpca.2013.6522303

Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) / Mar 01, 2016

Halpern, M., Zhu, Y., & Reddi, V. J. (2016). Mobile CPU’s rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction. 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 64–76. https://doi.org/10.1109/hpca.2016.7446054

Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) / Jun 01, 2007

Shye, A., Moseley, T., Reddi, V. J., Blomstedt, J., & Connors, D. A. (2007). Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance. 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’07), 297–306. https://doi.org/10.1109/dsn.2007.98

Voltage emergency prediction: Using signatures to reduce operating margins

2009 IEEE 15th International Symposium on High Performance Computer Architecture / Feb 01, 2009

Reddi, V. J., Gupta, M. S., Holloway, G., Wei, G.-Y., Smith, M. D., & Brooks, D. (2009). Voltage emergency prediction: Using signatures to reduce operating margins. 2009 IEEE 15th International Symposium on High Performance Computer Architecture, 18–29. https://doi.org/10.1109/hpca.2009.4798233

LatinX in AI at Neural Information Processing Systems Conference 2023

Dec 10, 2023

LatinX in AI at Neural Information Processing Systems Conference 2023. (2023, December 10). https://doi.org/10.52591/lxai202312100

Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) / Feb 01, 2015

Zhu, Y., Halpern, M., & Reddi, V. J. (2015, February). Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications. 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). https://doi.org/10.1109/hpca.2015.7056028

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture / Dec 01, 2010

Reddi, V. J., Kanev, S., Kim, W., Campanoni, S., Smith, M. D., Wei, G.-Y., & Brooks, D. (2010). Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling. 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 77–88. https://doi.org/10.1109/micro.2010.35

Shadow Profiling: Hiding Instrumentation Costs with Parallelism

International Symposium on Code Generation and Optimization (CGO'07) / Mar 01, 2007

Moseley, T., Shye, A., Reddi, V. J., Grunwald, D., & Peri, R. (2007). Shadow Profiling: Hiding Instrumentation Costs with Parallelism. International Symposium on Code Generation and Optimization (CGO’07), 198–208. https://doi.org/10.1109/cgo.2007.35

HELIX

Proceedings of the Tenth International Symposium on Code Generation and Optimization / Mar 31, 2012

Campanoni, S., Jones, T., Holloway, G., Reddi, V. J., Wei, G.-Y., & Brooks, D. (2012). HELIX: automatic parallelization of irregular programs for chip multiprocessing. Proceedings of the Tenth International Symposium on Code Generation and Optimization, 84–93. https://doi.org/10.1145/2259016.2259028

Education

PhD, Computer Architecture + AI Systems / October, 2010

Boston, Massachusetts, United States of America

Experience

Harvard University

Associate Professor / January, 2019Present

Links & Social Media

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