Principal Engineer / May, 2025 — Present

• Development and ownership of end-to-end Fan-Out Wafer-Level Packaging (FOWLP) production line for molded wafers and glass carriers for next-generation embedded components. • Lead vertical, 90-deg high aspect ratio die bonding and die stacking with thermal compression molding. • Drive installation, qualification and baseline for dicing, grinding, die attach, molding, ball attach, reflow, metrology systems. Technical advisor for front-end processes (dry etch, lithography, thin films, plating). • Establish high volume manufacturing process flows and statistically capable baselines for industry transfer. • Lead process and equipment development for internal and external customers with focus on rapid prototyping and HVM compatible transfer. • Technical owner for process integration, equipment readiness and risk management across multiple process flows.

Associate Faculty / January, 2025 — Present

Conducting a special topic on Semiconductor Manufacturing and Nanofabrication as a part of ASU workforce development program.

Graduate Research Associate / August, 2017 — October, 2022

PhD in Materials Science and Engineering (completed). • Extensive hands-on on development of the fabrication process to develop Porous Metal spherical powders and nanofilms. Experience chemical fabrication of semiconductor nanomaterials and structures with Metal-Assisted Chemical Etching (MACE) process with Hydrofluoric acid (HF). • Fabrication of porous metal structures and powders with a melting temperature suppression (1/3 of melting temperature of bulk). • Experience with 3D printing for fabrication of novel metal-infused structures. Development of a novel metal feedstock for Additive Manufacturing. • Procuring, installing and maintaining laboratory equipment (tube furnaces, glove box, magnetron sputtering, plasma cleaner, etc.). • Developing and maintaining safety culture white working with hazardous materials (HF, explosives, reactive materials). • >400 hours of hands-on work on the state-of-art metrology and inspection equipment (SEM, AFM, FIB, X-Ray, Raman, profilometry, etc.) • Experience writing scientific reports, papers and proposal. Development of IP for patent filing.

Packaging Module Development Engineer / November, 2022 — May, 2025

• Driving the development of advanced packaging analytical tools and techniques for Second Level Interconnect technology for BGA and PoINT products. Responsible for a successful start of 10+ products for both client and server space segment. • In-depth knowledge of process development practices (MBPS, DOE, MOR, etc.) and quality systems (SPC, FMEA, 8D). Knowledge of advanced statistical analysis practices to establish and monitor product process health. Knowledge of semiconductor device physics. • Strong ownership in driving product process health from the start of NPI to the product transfer readiness to multiple HVM sites. Embracing “pull yield curve left” mindset to enable robust process before the start of NPI. • Driving continuous improvement of key tools and processes for various EOL assembly operations. Writing and defining key BKMs, tool recipes and protocols for manufacturing equipment. Developing technical documentation and training materials for internal business practices and providing training to 50+ engineers and technicians. • Driving 2 year pathfinding project to enable new chemistry for 10M+ cost saving opportunities by reducing energy consumption and recovering electrically failing packages. Responsible for IP development and material qualification to enable state-of-the-art process in HVM compatible environment. • Conducting research and fundamental studies on materials, equipment, and fabrication processes to improve advanced semiconductor packaging technologies. • Developing strong working relationships with key stakeholders across multiple modules. • Ensuring strong cross-team collaboration to resolve IP and disclosure handling issues with external suppliers. Driving patent and disclosure writing for key development projects. Working with externalsuppliers to enable products with HVM capacity.

Senior Process Engineer / October, 2022 — May, 2025

Owned advanced packaging process development for BGA reflow and Patch on Interposer technology for legacy and 18A process nodes. Drove NPI readiness yield stabilization and manufacturing transfer across multiple sites. Defined process windows through SPC and DOE to reduce process variation and prevent excursions. Technical owner driving decision to resolve MRBDRB across TD and HVM sites. Led materials and chemistry pathfinding enabling recovery of electrically failing packages and reducing energy consumption delivering eight-figure annual cost savings. Led supplier technical alignment qualification strategy IP disclosures related to packaging process. Drove multiple invention disclosures for FOK technologies and process improvement.

Principal Semiconductor Packaging Engineer / May, 2025 — Present

Development and ownership of end-to-end Fan-Out Wafer-Level Packaging (FOWLP) production line for molded wafers and glass carriers for next-generation embedded components. Lead vertical 90-deg high aspect ratio die bonding and die stacking with thermal compression molding. Drive installation qualification and baseline for dicing grinding die attach molding ball attach reflow metrology systems. Technical advisor for front-end processes (dry etch lithography thin films plating). Establish high volume manufacturing process flows and statistically capable baselines for industry transfer. Lead process and equipment development for internal and external customers with focus on rapid prototyping and HVM compatible transfer. Technical owner for process integration equipment readiness and risk management across multiple process flows.

Graduate Research Associate / August, 2017 — October, 2022

Responsible for synthesis of inorganic nanostructured semiconductor and metallic materials design and development of research experiments for chemistry electrochemistry additive manufacturing and multimaterial 3D printing for energetics. The primary focus is on SPC control in nanostructured thin metallic films and mesoscale powders and analysis of its structural chemical and optical properties. Development of disintegrable explosive materials for military applications. Instructing a 500-level course to a group of 30 undergraduate and graduate students from various cultural and educational backgrounds. Developing constructing and communicating the material on various topics in Semiconductor Manufacturing Silicon Photonics and Solid State Physics.