Naveed Khan

Assistant Professor in Computer Engineering Department with publications in Network on Chip, ML, and AI at UET

Research Expertise

Embedded Systems
Digital Design
On-Chip networks
Fault tolerant designs
Self healing systems

About

Naveed Khan is an accomplished Artificial Intelligence expert with a strong academic background and years of experience in the field. He holds a Ph.D in Artificial Intelligence from a prestigious institution and has published several research papers in top journals. Naveed has also worked as an Assistant Professor at the University of Engineering and Technology Taxila, where he taught courses on AI and supervised student research projects. His expertise is machine learning, natural language processing, and computer vision. Naveed is passionate about using AI to solve real-world problems and constantly seeks new challenges and opportunities to expand his knowledge and skills. His strong academic and professional background makes him a valuable asset to any organization looking to advance its AI capabilities.

Publications

Impact of Feature Selection Algorithm on Speech Emotion Recognition Using Deep Convolutional Neural Network
Sensors
2020
Incorporating Noise Robustness in Speech Command Recognition by Noise Augmentation of Training Data
Sensors
2020
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
IEEE Access
2020
Improving Mispronunciation Detection of Arabic Words for Non-Native Learners Using Deep Convolutional Neural Network Features
Electronics
2020
Fingerprint verification over the network and its application in attendance management
2010 International Conference on Electronics and Information Engineering
2010
Supervised Machine Learning based Fast Hand Gesture Recognition and Classification Using Electromyography (EMG) Signals
2021 International Conference on Applied and Engineering Mathematics (ICAEM)
2021
NoCGuard: A Reliable Network-on-Chip Router Architecture
Electronics
2020
An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication
Software: Practice and Experience
2020
Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things
Sensors
2020
Defender: A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router
IEEE Access
2019
Design Trade off and Performance Analysis of Router Architectures in Network-on-Chip
Procedia Computer Science
2015
Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip
Electronics
2020
Protector: A Permanent Fault Resilient Router Architecture for Network on Chip
Mehran University Research Journal of Engineering and Technology
2020
3D-HEVC Neighboring Block Based Disparity Vector (NBDV) Derivation Architecture: Complexity and Implementation Analysis
Lecture Notes in Electrical Engineering
2020
High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems
2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
2013
Fault-Aware Dual-Layer Adaptive Error Control Technique for NoC
The Smart Computing Review
2015
Dynamic Grouping Frame-Slotted Aloha
International Journal of Computer Applications
2012
Multi-bit Error Correction Technique for NTC based Network on Chip
AEBMS-2017, ICCET-2017, BBMPS-17, UPACEE-17, LHESS-17, TBFIS-2017, IC4E-2017, AMLIS-2017 & BEFM-2017
2018

Education

Ph.D, Artificial Intelligence / November, 2020

Taxila

Experience

University of Engineering and Technology Taxila

Assistant Professor / March — 2009

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