David J. Lilja

Professor Emeritus of Electrical and Computer Engineering, University of Minnesota

Minneapolis, Minnesota, United States of America

Research Expertise

Computer architecture
high-performance parallel processing
computer systems performance analysis
approximate computing
Hardware and Architecture
Software
Electrical and Electronic Engineering
Signal Processing
Information Systems
Computers in Earth Sciences
Computer Networks and Communications
Computer Science Applications
Education
storage systems
faculty development
curriculum review

About

**Research Expertise** Computer architecture, high-performance parallel processing, computer systems performance analysis, approximate computing, computing with emerging technologies, and storage systems. **Biographical summary** David J. Lilja received a Ph.D. and an M.S., both in Electrical Engineering, from the [University of Illinois at Urbana-Champaign,](http://www.uiuc.edu/) and a B.S. in Computer Engineering from [Iowa State University](http://www.iastate.edu/) in Ames. He is Professor Emeritus of [Electrical and Computer Engineering](http://www.ee.umn.edu/) at the [University of Minnesota](http://www.umn.edu/) in Minneapolis. He previously served as a member of the graduate faculties in [Computer Science](http://www.cs.umn.edu/), [Scientific Computation](http://www.scicomp.umn.edu/), and [Data Science](http://datascience.umn.edu//).  He served ten years as the head of the ECE department at the University of Minnesota, worked as a research assistant at the Center for Supercomputing Research and Development at the [University of Illinois,](http://www.uiuc.edu/) and as a development engineer at [Tandem Computers Incorporated](http://www.tandem.com/) in Cupertino, California.  He received a [Fulbright](http://www.fulbright.org/) Senior Scholar Award to visit the University of Western Australia and was a visiting Professor at the University of Canterbury in Christchurch, New Zealand. He has chaired and served on the program committees of numerous conferences.  He was elected a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and a Fellow of the American Association for the Advancement of Science (AAAS) for contributions to the statistical analysis of computer performance. He also is a registered Professional Engineer.

Publications

Measuring Computer Performance

Jul 20, 2000

Lilja, D. J. (2000). Measuring Computer Performance: A Practitioner’s Guide. Cambridge University Press. https://doi.org/10.1017/cbo9780511612398

MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research

IEEE Computer Architecture Letters / Jan 01, 2002

KleinOsowski, A. J., & Lilja, D. J. (2002). MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. IEEE Computer Architecture Letters, 1(1), 7–7. https://doi.org/10.1109/l-ca.2002.8

An Architecture for Fault-Tolerant Computation with Stochastic Logic

IEEE Transactions on Computers / Jan 01, 2011

Qian, W., Li, X., Riedel, M. D., Bazargan, K., & Lilja, D. J. (2011). An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Transactions on Computers, 60(1), 93–105. https://doi.org/10.1109/tc.2010.202

BloomFlash: Bloom Filter on Flash-Based Storage

2011 31st International Conference on Distributed Computing Systems / Jun 01, 2011

Debnath, B., Sengupta, S., Li, J., Lilja, D. J., & Du, D. H. C. (2011, June). BloomFlash: Bloom Filter on Flash-Based Storage. 2011 31st International Conference on Distributed Computing Systems. https://doi.org/10.1109/icdcs.2011.44

Data prefetch mechanisms

ACM Computing Surveys / Jun 01, 2000

Vanderwiel, S. P., & Lilja, D. J. (2000). Data prefetch mechanisms. ACM Computing Surveys, 32(2), 174–199. https://doi.org/10.1145/358923.358939

Computation on Stochastic Bit Streams Digital Image Processing Case Studies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems / Mar 01, 2014

Li, P., Lilja, D. J., Qian, W., Bazargan, K., & Riedel, M. D. (2014). Computation on Stochastic Bit Streams Digital Image Processing Case Studies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(3), 449–462. https://doi.org/10.1109/tvlsi.2013.2247429

The superthreaded processor architecture

IEEE Transactions on Computers / Jan 01, 1999

Jenn-Yuan Tsai, Jian Huang, Amlo, C., Lilja, D. J., & Pen-Chung Yew. (1999). The superthreaded processor architecture. IEEE Transactions on Computers, 48(9), 881–902. https://doi.org/10.1109/12.795219

Accelerating Lattice Boltzmann Fluid Flow Simulations Using Graphics Processors

2009 International Conference on Parallel Processing / Sep 01, 2009

Bailey, P., Myre, J., Walsh, S. D. C., Lilja, D. J., & Saar, M. O. (2009, September). Accelerating Lattice Boltzmann Fluid Flow Simulations Using Graphics Processors. 2009 International Conference on Parallel Processing. https://doi.org/10.1109/icpp.2009.38

Cache coherence in large-scale shared-memory multiprocessors

ACM Computing Surveys / Sep 01, 1993

Lilja, D. J. (1993). Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons. ACM Computing Surveys, 25(3), 303–338. https://doi.org/10.1145/158439.158907

Using stochastic computing to implement digital image processing algorithms

2011 IEEE 29th International Conference on Computer Design (ICCD) / Oct 01, 2011

Li, P., & Lilja, D. J. (2011, October). Using stochastic computing to implement digital image processing algorithms. 2011 IEEE 29th International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2011.6081391

A statistically rigorous approach for improving simulation methodology

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.

Yi, J. J., Lilja, D. J., & Hawkins, D. M. (n.d.). A statistically rigorous approach for improving simulation methodology. The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. https://doi.org/10.1109/hpca.2003.1183546

Exploiting basic block value locality with block reuse

Proceedings Fifth International Symposium on High-Performance Computer Architecture / Jan 01, 1999

Jian Huang, & Lilja, D. J. (1999). Exploiting basic block value locality with block reuse. Proceedings Fifth International Symposium on High-Performance Computer Architecture. https://doi.org/10.1109/hpca.1999.744342

Challenges in computer architecture evaluation

Computer / Aug 01, 2003

Skadron, K., Martonosi, M., August, D. I., Hill, M. D., Lilja, D. J., & Pai, V. S. (2003). Challenges in computer architecture evaluation. Computer, 36(8), 30–36. https://doi.org/10.1109/mc.2003.1220579

Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations

IEEE Transactions on Computers / Mar 01, 2006

Yi, J. J., & Lilja, D. J. (2006). Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations. IEEE Transactions on Computers, 55(3), 268–280. https://doi.org/10.1109/tc.2006.44

When caches aren't enough: data prefetching techniques

Computer / Jul 01, 1997

Vander Wiel, S. P., & Lilja, D. J. (1997). When caches aren’t enough: data prefetching techniques. Computer, 30(7), 23–30. https://doi.org/10.1109/2.596622

Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research

Workload Characterization of Emerging Computer Applications / Jan 01, 2001

KleinOsowski, A. J., Flynn, J., Meares, N., & Lilja, D. J. (2001). Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research. In Workload Characterization of Emerging Computer Applications (pp. 83–100). Springer US. https://doi.org/10.1007/978-1-4615-1613-2_4

Characterizing and Comparing Prevailing Simulation Techniques

11th International Symposium on High-Performance Computer Architecture

Joshua J. Yi, Kodakara, S. V., Sendag, R., Lilja, D. J., & Hawkins, D. M. (n.d.). Characterizing and Comparing Prevailing Simulation Techniques. 11th International Symposium on High-Performance Computer Architecture. https://doi.org/10.1109/hpca.2005.8

Exploiting the parallelism available in loops

Computer / Feb 01, 1994

Lilja, D. J. (1994). Exploiting the parallelism available in loops. Computer, 27(2), 13–26. https://doi.org/10.1109/2.261915

Wireless sensor network for aircraft health monitoring

First International Conference on Broadband Networks

Haowei Bai, Atiquzzaman, M., & Lilja, D. (n.d.). Wireless sensor network for aircraft health monitoring. First International Conference on Broadband Networks. https://doi.org/10.1109/broadnets.2004.92

So many states, so little time: verifying memory coherence in the Cray X1

Proceedings International Parallel and Distributed Processing Symposium

Abts, D., Scott, S., & Lilja, D. J. (n.d.). So many states, so little time: verifying memory coherence in the Cray X1. Proceedings International Parallel and Distributed Processing Symposium. https://doi.org/10.1109/ipdps.2003.1213087

Techniques for obtaining high performance in Java programs

ACM Computing Surveys / Sep 01, 2000

Kazi, I. H., Chen, H. H., Stanley, B., & Lilja, D. J. (2000). Techniques for obtaining high performance in Java programs. ACM Computing Surveys, 32(3), 213–240. https://doi.org/10.1145/367701.367714

Characterization of communication patterns in message-passing parallel scientific application programs

Lecture Notes in Computer Science / Jan 01, 1998

Kim, J., & Lilja, D. J. (1998). Characterization of communication patterns in message-passing parallel scientific application programs. In Network-Based Parallel Computing Communication, Architecture, and Applications (pp. 202–216). Springer Berlin Heidelberg. https://doi.org/10.1007/bfb0052218

SARD: A statistical approach for ranking database tuning parameters

2008 IEEE 24th International Conference on Data Engineering Workshop / Apr 01, 2008

Debnath, B. K., Lilja, D. J., & Mokbel, M. F. (2008, April). SARD: A statistical approach for ranking database tuning parameters. 2008 IEEE 24th International Conference on Data Engineering Workshop. https://doi.org/10.1109/icdew.2008.4498279

The future of simulation: a field of dreams

Computer / Nov 01, 2006

Yi, J. J., Eeckhout, L., Lilja, D. J., Calder, B., John, L. K., & Smith, J. E. (2006). The future of simulation: a field of dreams. Computer, 39(11), 22–29. https://doi.org/10.1109/mc.2006.404

Dynamic scheduling techniques for heterogeneous computing systems

Concurrency: Practice and Experience / Oct 01, 1995

Hamidzadeh, B., Atif, Y., & Lilja, D. J. (1995). Dynamic scheduling techniques for heterogeneous computing systems. Concurrency: Practice and Experience, 7(7), 633–652. Portico. https://doi.org/10.1002/cpe.4330070705

Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines

IEEE Transactions on Computers / Jun 01, 2014

Li, P., Lilja, D. J., Qian, W., Riedel, M. D., & Bazargan, K. (2014). Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines. IEEE Transactions on Computers, 63(6), 1474–1486. https://doi.org/10.1109/tc.2012.231

Dynamic task scheduling using online optimization

IEEE Transactions on Parallel and Distributed Systems / Jan 01, 2000

Lilja, D. J., Lau Ying Kit, & Hamidzadeh, B. (2000). Dynamic task scheduling using online optimization. IEEE Transactions on Parallel and Distributed Systems, 11(11), 1151–1163. https://doi.org/10.1109/71.888636

Direct communication between magnetic tunnel junctions for nonvolatile logic fan-out architecture

Applied Physics Letters / Oct 11, 2010

Lyle, A., Harms, J., Patil, S., Yao, X., Lilja, D. J., & Wang, J.-P. (2010). Direct communication between magnetic tunnel junctions for nonvolatile logic fan-out architecture. Applied Physics Letters, 97(15). https://doi.org/10.1063/1.3499427

High performance solid state storage under Linux

2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST) / May 01, 2010

Seppane, E., O’Keefe, M. T., & Lilja, D. J. (2010, May). High performance solid state storage under Linux. 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST). https://doi.org/10.1109/msst.2010.5496976

Accelerating geoscience and engineering system simulations on graphics hardware

Computers & Geosciences / Dec 01, 2009

Walsh, S. D. C., Saar, M. O., Bailey, P., & Lilja, D. J. (2009). Accelerating geoscience and engineering system simulations on graphics hardware. Computers & Geosciences, 35(12), 2353–2364. https://doi.org/10.1016/j.cageo.2009.05.001

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic

Proceedings of the International Conference on Computer-Aided Design / Nov 05, 2012

Li, P., Lilja, D. J., Qian, W., Bazargan, K., & Riedel, M. (2012, November 5). The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. Proceedings of the International Conference on Computer-Aided Design. https://doi.org/10.1145/2429384.2429483

A Hardware Implementation of a Radial Basis Function Neural Network Using Stochastic Logic

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 / Jan 01, 2015

Ji, Y., Ran, F., Ma, C., & Lilja, D. J. (2015). A Hardware Implementation of a Radial Basis Function Neural Network Using Stochastic Logic. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. https://doi.org/10.7873/date.2015.0377

Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) / Mar 01, 2019

Faraji, S. R., Hassan Najafi, M., Li, B., Lilja, D. J., & Bazargan, K. (2019, March). Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing. 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). https://doi.org/10.23919/date.2019.8714937

Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays / Feb 21, 2016

Li, B., Najafi, M. H., & Lilja, D. J. (2016, February 21). Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier. Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. https://doi.org/10.1145/2847263.2847340

Performing Stochastic Computation Deterministically

IEEE Transactions on Very Large Scale Integration (VLSI) Systems / Dec 01, 2019

Najafi, M. H., Jenson, D., Lilja, D. J., & Riedel, M. D. (2019). Performing Stochastic Computation Deterministically. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(12), 2925–2938. https://doi.org/10.1109/tvlsi.2019.2929354

Low-Cost Sorting Network Circuits Using Unary Processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems / Aug 01, 2018

Najafi, M. H., Lilja, David. J., Riedel, M. D., & Bazargan, K. (2018). Low-Cost Sorting Network Circuits Using Unary Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8), 1471–1480. https://doi.org/10.1109/tvlsi.2018.2822300

IIR filters using stochastic arithmetic

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 / Jan 01, 2014

Saraf, N., Bazargan, K., Lilja, D. J., & Riedel, M. D. (2014). IIR filters using stochastic arithmetic. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. https://doi.org/10.7873/date.2014.086

Time-Encoded Values for Highly Efficient Stochastic Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems / May 01, 2017

Najafi, M. H., Jamali-Zavareh, S., Lilja, D. J., Riedel, M. D., Bazargan, K., & Harjani, R. (2017). Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(5), 1644–1657. https://doi.org/10.1109/tvlsi.2016.2645902

Deterministic methods for stochastic computing using low-discrepancy sequences

Proceedings of the International Conference on Computer-Aided Design / Nov 05, 2018

Najafi, M. H., Lilja, D. J., & Riedel, M. (2018, November 5). Deterministic methods for stochastic computing using low-discrepancy sequences. Proceedings of the International Conference on Computer-Aided Design. https://doi.org/10.1145/3240765.3240797

Approximate Communication

ACM Computing Surveys / Jan 10, 2018

Betzel, F., Khatamifard, K., Suresh, H., Lilja, D. J., Sartori, J., & Karpuzcu, U. (2018). Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems. ACM Computing Surveys, 51(1), 1–32. https://doi.org/10.1145/3145812

Characterizing datasets for data deduplication in backup applications

IEEE International Symposium on Workload Characterization (IISWC'10) / Dec 01, 2010

Park, N., & Lilja, D. J. (2010, December). Characterizing datasets for data deduplication in backup applications. IEEE International Symposium on Workload Characterization (IISWC’10). https://doi.org/10.1109/iiswc.2010.5650369

Trends in shared memory multiprocessing

Computer / Jan 01, 1997

Stenstrom, P., Hagersten, E., Lilja, D. J., Martonosi, M., & Venugopal, M. (1997). Trends in shared memory multiprocessing. Computer, 30(12), 44–50. https://doi.org/10.1109/2.642814

Performance analysis of single‐phase, multiphase, and multicomponent lattice‐Boltzmann fluid flow simulations on GPU clusters

Concurrency and Computation: Practice and Experience / Sep 24, 2010

Myre, J., Walsh, S. D. C., Lilja, D., & Saar, M. O. (2010). Performance analysis of single‐phase, multiphase, and multicomponent lattice‐Boltzmann fluid flow simulations on GPU clusters. Concurrency and Computation: Practice and Experience, 23(4), 332–350. Portico. https://doi.org/10.1002/cpe.1645

The synthesis of linear Finite State Machine-based Stochastic Computational Elements

17th Asia and South Pacific Design Automation Conference / Jan 01, 2012

Peng Li, Qian, W., Riedel, M. D., Bazargan, K., & Lilja, D. J. (2012, January). The synthesis of linear Finite State Machine-based Stochastic Computational Elements. 17th Asia and South Pacific Design Automation Conference. https://doi.org/10.1109/aspdac.2012.6165056

JaViz: A client/server Java profiling tool

IBM Systems Journal / Jan 01, 2000

Kazi, I. H., Jose, D. P., Ben-Hamida, B., Hescott, C. J., Kwok, C., Konstan, J. A., Lilja, D. J., & Yew, P.-C. (2000). JaViz: A client/server Java profiling tool. IBM Systems Journal, 39(1), 96–117. https://doi.org/10.1147/sj.391.0096

Large Block CLOCK (LB-CLOCK): A write caching algorithm for solid state disks

2009 IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems / Sep 01, 2009

Debnath, B., Subramanya, S., Du, D., & Lilja, D. J. (2009, September). Large Block CLOCK (LB-CLOCK): A write caching algorithm for solid state disks. 2009 IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems. https://doi.org/10.1109/mascot.2009.5366737

Improving processor performance by simplifying and bypassing trivial computations

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

Yi, J. J., & Lilja, D. J. (n.d.). Improving processor performance by simplifying and bypassing trivial computations. Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors. https://doi.org/10.1109/iccd.2002.1106814

Extending value reuse to basic blocks with compiler support

IEEE Transactions on Computers / Apr 01, 2000

Huang, J., & Lilja, D. J. (2000). Extending value reuse to basic blocks with compiler support. IEEE Transactions on Computers, 49(4), 331–347. https://doi.org/10.1109/12.844346

Designing Digital Computer Systems with Verilog

Dec 02, 2004

Lilja, D. J., & Sapatnekar, S. S. (2004). Designing Digital Computer Systems with Verilog. Cambridge University Press. https://doi.org/10.1017/cbo9780511607059

Microarchitecture-aware floorplanning using a statistical design of experiments approach

Proceedings. 42nd Design Automation Conference, 2005. / Jan 01, 2005

Nookala, V., Ying Chen, Lilja, D. J., & Sapatnekar, S. S. (2005). Microarchitecture-aware floorplanning using a statistical design of experiments approach. Proceedings. 42nd Design Automation Conference, 2005. https://doi.org/10.1109/dac.2005.193877

A compiler-assisted data prefetch controller

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)

Vander Wiel, S. P., & Lilja, D. J. (n.d.). A compiler-assisted data prefetch controller. Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040). https://doi.org/10.1109/iccd.1999.808569

The synthesis of combinational logic to generate probabilities

Proceedings of the 2009 International Conference on Computer-Aided Design / Nov 02, 2009

Qian, W., Riedel, M. D., Bazargan, K., & Lilja, D. J. (2009, November 2). The synthesis of combinational logic to generate probabilities. Proceedings of the 2009 International Conference on Computer-Aided Design. https://doi.org/10.1145/1687399.1687470

Self-Adjusting Scheduling: An On-Line Optimization Technique for Locality Management and Load Balancing

1994 International Conference on Parallel Processing (ICPP'94) / Aug 01, 1994

Hamidzadeh, B., & Lilja, D. (1994, August). Self-Adjusting Scheduling: An On-Line Optimization Technique for Locality Management and Load Balancing. 1994 International Conference on Parallel Processing (ICPP’94). https://doi.org/10.1109/icpp.1994.179

A reconfigurable stochastic architecture for highly reliable computing

Proceedings of the 19th ACM Great Lakes symposium on VLSI / May 10, 2009

Li, X., Qian, W., Riedel, M. D., Bazargan, K., & Lilja, D. J. (2009, May 10). A reconfigurable stochastic architecture for highly reliable computing. Proceedings of the 19th ACM Great Lakes Symposium on VLSI. https://doi.org/10.1145/1531542.1531615

Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor

IEEE Transactions on Computers / Nov 01, 2005

Yi, J. J., Lilja, D. J., & Hawkins, D. M. (2005). Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor. IEEE Transactions on Computers, 54(11), 1360–1373. https://doi.org/10.1109/tc.2005.184

Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function

2017 IEEE International Conference on Computer Design (ICCD) / Nov 01, 2017

Li, B., Qin, Y., Yuan, B., & Lilja, D. J. (2017, November). Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function. 2017 IEEE International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2017.23

Magnetic Tunnel Junction Logic Architecture for Realization of Simultaneous Computation and Communication

IEEE Transactions on Magnetics / Oct 01, 2011

Lyle, A., Patil, S., Harms, J., Glass, B., Yao, X., Lilja, D., & Wang, J.-P. (2011). Magnetic Tunnel Junction Logic Architecture for Realization of Simultaneous Computation and Communication. IEEE Transactions on Magnetics, 47(10), 2970–2973. https://doi.org/10.1109/tmag.2011.2158527

An effective processor allocation strategy for multiprogrammed shared-memory multiprocessors

IEEE Transactions on Parallel and Distributed Systems / Jan 01, 1997

Yue, K. K., & Lilja, D. J. (1997). An effective processor allocation strategy for multiprogrammed shared-memory multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 8(12), 1246–1258. https://doi.org/10.1109/71.640017

Instruction prefetching of systems codes with layout optimized for reduced cache misses

Proceedings of the 23rd annual international symposium on Computer architecture / May 01, 1996

Xia, C., & Torrellas, J. (1996, May). Instruction prefetching of systems codes with layout optimized for reduced cache misses. Proceedings of the 23rd Annual International Symposium on Computer Architecture. https://doi.org/10.1145/232973.233001

Spintronic logic gates for spintronic data using magnetic tunnel junctions

2010 IEEE International Conference on Computer Design / Oct 01, 2010

Patil, S., Lyle, A., Harms, J., Lilja, D. J., & Wang, J.-P. (2010, October). Spintronic logic gates for spintronic data using magnetic tunnel junctions. 2010 IEEE International Conference on Computer Design. https://doi.org/10.1109/iccd.2010.5647611

Coarse-grained speculative execution in shared-memory multiprocessors

Proceedings of the 12th international conference on Supercomputing / Jul 13, 1998

Kazi, I. H., & Lilja, D. J. (1998, July 13). Coarse-grained speculative execution in shared-memory multiprocessors. Proceedings of the 12th International Conference on Supercomputing. https://doi.org/10.1145/277830.277853

Von Neumann Computers

Wiley Encyclopedia of Electrical and Electronics Engineering / Dec 27, 1999

Eigenmann, R., & Lilja, D. J. (1999, December 27). Von Neumann Computers. Wiley Encyclopedia of Electrical and Electronics Engineering; Wiley; Portico. https://doi.org/10.1002/047134608x.w1704

Complexity and performance in parallel programming languages

Proceedings Second International Workshop on High-Level Parallel Programming Models and Supportive Environments

VanderWiel, S. P., Nathanson, D., & Lilja, D. J. (n.d.). Complexity and performance in parallel programming languages. Proceedings Second International Workshop on High-Level Parallel Programming Models and Supportive Environments. https://doi.org/10.1109/hips.1997.582951

Exploring Performance Characteristics of the Optane 3D Xpoint Storage Technology

ACM Transactions on Modeling and Performance Evaluation of Computing Systems / Feb 04, 2020

Yang, J., Li, B., & Lilja, D. J. (2020). Exploring Performance Characteristics of the Optane 3D Xpoint Storage Technology. ACM Transactions on Modeling and Performance Evaluation of Computing Systems, 5(1), 1–28. https://doi.org/10.1145/3372783

An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) / Jul 01, 2015

Li, B., Najafi, M. H., & Lilja, D. J. (2015, July). An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams. 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP). https://doi.org/10.1109/asap.2015.7245709

A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm

ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors / Sep 01, 2011

Li, P., & Lilja, D. J. (2011, September). A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm. ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors. https://doi.org/10.1109/asap.2011.6043264

Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis

Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06 / Jan 01, 2006

Nookala, V., Lilja, D. J., & Sapatnekar, S. S. (2006). Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED ’06. https://doi.org/10.1145/1165573.1165644

Evaluating Benchmark Subsetting Approaches

2006 IEEE International Symposium on Workload Characterization / Oct 01, 2006

Yi, J., Sendag, R., Eeckhout, L., Joshi, A., Lilja, D., & John, L. (2006, October). Evaluating Benchmark Subsetting Approaches. 2006 IEEE International Symposium on Workload Characterization. https://doi.org/10.1109/iiswc.2006.302733

Changing interaction of compiler and architecture

Computer / Jan 01, 1997

Adve, S. V., Burger, D., Eigenmann, R., Rawsthorne, A., Smith, M. D., Gebotys, C. H., Kandemir, M. T., Lilja, D. J., Choudbary, A. N., Fang, J. Z., & Pen-Chung Yew. (1997). Changing interaction of compiler and architecture. Computer, 30(12), 51–58. https://doi.org/10.1109/2.642815

Quantized neural networks with new stochastic multipliers

2018 19th International Symposium on Quality Electronic Design (ISQED) / Mar 01, 2018

Li, B., Najafi, M. H., Yuan, B., & Lilja, D. J. (2018, March). Quantized neural networks with new stochastic multipliers. 2018 19th International Symposium on Quality Electronic Design (ISQED). https://doi.org/10.1109/isqed.2018.8357316

US patent depository libraries programme

World Patent Information / Jan 01, 1989

US patent depository libraries programme. (1989). World Patent Information, 11(3), 174. https://doi.org/10.1016/0172-2190(89)90152-x

Romano

Proceedings of the Third ACM Symposium on Cloud Computing / Oct 14, 2012

Park, N., Ahmad, I., & Lilja, D. J. (2012, October 14). Romano: autonomous storage management using performance prediction in multi-tenant datacenters. Proceedings of the Third ACM Symposium on Cloud Computing. https://doi.org/10.1145/2391229.2391250

Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) / Jul 01, 2018

Yang, M., Li, B., Lilja, D. J., Yuan, B., & Qian, W. (2018, July). Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). https://doi.org/10.1109/isvlsi.2018.00037

High Quality Down-Sampling for Deterministic Approaches to Stochastic Computing

IEEE Transactions on Emerging Topics in Computing / Jan 01, 2021

Najafi, M. H., & Lilja, D. J. (2021). High Quality Down-Sampling for Deterministic Approaches to Stochastic Computing. IEEE Transactions on Emerging Topics in Computing, 9(1), 7–14. https://doi.org/10.1109/tetc.2017.2789243

A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic

2012 IEEE 30th International Conference on Computer Design (ICCD) / Sep 01, 2012

Li, P., Qian, W., & Lilja, D. J. (2012, September). A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic. 2012 IEEE 30th International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2012.6378656

Comparing Exact and Approximate Spatial Auto-regression Model Solutions for Spatial Data Analysis

Geographic Information Science / Jan 01, 2004

Kazar, B. M., Shekhar, S., Lilja, D. J., Vatsavai, R. R., & Pace, R. K. (2004). Comparing Exact and Approximate Spatial Auto-regression Model Solutions for Spatial Data Analysis. In Lecture Notes in Computer Science (pp. 140–161). Springer Berlin Heidelberg. https://doi.org/10.1007/978-3-540-30231-5_10

Teaching computer systems performance analysis

IEEE Transactions on Education / Jan 01, 2001

Lilja, D. J. (2001). Teaching computer systems performance analysis. IEEE Transactions on Education, 44(1), 35–40. https://doi.org/10.1109/13.912708

Memory module-level testing and error behaviors for phase change memory

2012 IEEE 30th International Conference on Computer Design (ICCD) / Sep 01, 2012

Zhang, Z., Xiao, W., Park, N., & Lilja, D. J. (2012, September). Memory module-level testing and error behaviors for phase change memory. 2012 IEEE 30th International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2012.6378664

JavaSpMT: A speculative thread pipelining parallelization model for Java programs

Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000

Kazi, I. H., & Lilja, D. J. (n.d.). JavaSpMT: A speculative thread pipelining parallelization model for Java programs. Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000. https://doi.org/10.1109/ipdps.2000.846035

Accurate statistical approaches for generating representative workload compositions

IEEE International. 2005 Proceedings of the IEEE Workload Characterization Symposium, 2005.

Eeckhout, L., Sundareswara, R., Joshua J. Yi, Lilja, D. J., & Schrater, P. (n.d.). Accurate statistical approaches for generating representative workload compositions. IEEE International. 2005 Proceedings of the IEEE Workload Characterization Symposium, 2005. https://doi.org/10.1109/iiswc.2005.1526001

Dynamic scheduling strategies for shared-memory multiprocessors

Proceedings of 16th International Conference on Distributed Computing Systems

Hamidzadeh, B., & Lilja, D. J. (n.d.). Dynamic scheduling strategies for shared-memory multiprocessors. Proceedings of 16th International Conference on Distributed Computing Systems. https://doi.org/10.1109/icdcs.1996.507918

The potential of compile-time analysis to adapt the cache coherence enforcement strategy to the data sharing characteristics

IEEE Transactions on Parallel and Distributed Systems / May 01, 1995

Mounes-Toussi, F., & Lilja, D. J. (1995). The potential of compile-time analysis to adapt the cache coherence enforcement strategy to the data sharing characteristics. IEEE Transactions on Parallel and Distributed Systems, 6(5), 470–481. https://doi.org/10.1109/71.382316

Spin-Hall effect MRAM based cache memory: A feasibility study

2015 73rd Annual Device Research Conference (DRC) / Jun 01, 2015

Kim, J., Tuohy, B., Ma, C., Choi, W. H., Ahmed, I., Lilja, D., & Kim, C. H. (2015, June). Spin-Hall effect MRAM based cache memory: A feasibility study. 2015 73rd Annual Device Research Conference (DRC). https://doi.org/10.1109/drc.2015.7175583

Buffer Requirements at ECN-Capable RED Gateways to Minimize Packet Losses

2005 IEEE International Conference on Electro Information Technology

Haowei Bai, & Lilja, D. (n.d.). Buffer Requirements at ECN-Capable RED Gateways to Minimize Packet Losses. 2005 IEEE International Conference on Electro Information Technology. https://doi.org/10.1109/eit.2005.1627009

The NanoBox project: exploring fabrics of self-correcting logic blocks for high defect rate molecular device technologies

IEEE Computer Society Annual Symposium on VLSI

KleinOsowski, A. J., & Lilja, D. J. (n.d.). The NanoBox project: exploring fabrics of self-correcting logic blocks for high defect rate molecular device technologies. IEEE Computer Society Annual Symposium on VLSI. https://doi.org/10.1109/isvlsi.2004.1339503

Combining hardware and software cache coherence strategies

Proceedings of the 5th international conference on Supercomputing - ICS '91 / Jan 01, 1991

Lilja, D. J., & Yew, P.-C. (1991). Combining hardware and software cache coherence strategies. Proceedings of the 5th International Conference on Supercomputing - ICS ’91. https://doi.org/10.1145/109025.109093

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Euro-Par 2002 Parallel Processing / Jan 01, 2002

Sendag, R., Lilja, D. J., & Kunkel, S. R. (2002). Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions. In Lecture Notes in Computer Science (pp. 468–480). Springer Berlin Heidelberg. https://doi.org/10.1007/3-540-45706-2_64

TNT-NN: A Fast Active Set Method for Solving Large Non-Negative Least Squares Problems

Procedia Computer Science / Jan 01, 2017

Myre, J. M., Frahm, E., Lilja, D. J., & Saar, M. O. (2017). TNT-NN: A Fast Active Set Method for Solving Large Non-Negative Least Squares Problems. Procedia Computer Science, 108, 755–764. https://doi.org/10.1016/j.procs.2017.05.194

PASS: A Hybrid Storage System for Performance-Synchronization Tradeoffs Using SSDs

2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications / Jul 01, 2012

Xiao, W., Lei, X., Li, R., Park, N., & Lilja, D. J. (2012, July). PASS: A Hybrid Storage System for Performance-Synchronization Tradeoffs Using SSDs. 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications. https://doi.org/10.1109/ispa.2012.59

Using incorrect speculation to prefetch data in a concurrent multithreaded processor

Proceedings International Parallel and Distributed Processing Symposium

Ying Chen, Sendag, R., & Lija, D. J. (n.d.). Using incorrect speculation to prefetch data in a concurrent multithreaded processor. Proceedings International Parallel and Distributed Processing Symposium. https://doi.org/10.1109/ipdps.2003.1213177

Coarse-grained thread pipelining: a speculative parallel execution model for shared-memory multiprocessors

IEEE Transactions on Parallel and Distributed Systems / Sep 01, 2001

Kazi, I. H., & Lilja, D. J. (2001). Coarse-grained thread pipelining: a speculative parallel execution model for shared-memory multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 12(9), 952–966. https://doi.org/10.1109/71.954629

Exploring sub-block value reuse for superscalar processors

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

Jian Huang, & Lilja, D. J. (n.d.). Exploring sub-block value reuse for superscalar processors. Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622). https://doi.org/10.1109/pact.2000.888335

Instruction-level parallelism in Prolog

Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92 / Jan 01, 1992

De Gloria, A., & Faraboschi, P. (1992). Instruction-level parallelism in Prolog: analysis and architectural support. Proceedings of the 19th Annual International Symposium on Computer Architecture - ISCA ’92. https://doi.org/10.1145/139669.139730

Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics

IEEE Computer Architecture Letters / Jan 01, 2010

Patil, S., & Lilja, D. J. (2010). Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics. IEEE Computer Architecture Letters, 9(1), 1–4. https://doi.org/10.1109/l-ca.2010.1

Evaluating the efficacy of statistical simulation for design space exploration

2006 IEEE International Symposium on Performance Analysis of Systems and Software

Joshi, A., Yi, J. J., Bell, R. H., Eeckhout, L., John, L., & Lilja, D. (n.d.). Evaluating the efficacy of statistical simulation for design space exploration. 2006 IEEE International Symposium on Performance Analysis of Systems and Software. https://doi.org/10.1109/ispass.2006.1620791

Efficient execution of parallel applications in multiprogrammed multiprocessor systems

Proceedings of International Conference on Parallel Processing

Yue, K. K., & Lilja, D. J. (n.d.). Efficient execution of parallel applications in multiprogrammed multiprocessor systems. Proceedings of International Conference on Parallel Processing. https://doi.org/10.1109/ipps.1996.508094

High-speed stochastic circuits using synchronous analog pulses

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) / Jan 01, 2017

Najafi, M. H., & Lilja, D. J. (2017, January). High-speed stochastic circuits using synchronous analog pulses. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). https://doi.org/10.1109/aspdac.2017.7858369

Linear Regression Using R: An Introduction to Data Modeling

Jan 01, 2016

Lilja, D. (2016). Linear Regression Using R: An Introduction to Data Modeling. University of Minnesota Libraries Publishing. https://doi.org/10.24926/8668/1301

Kinetic Action: Performance Analysis of Integrated Key-Value Storage Devices vs. LevelDB Servers

2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS) / Dec 01, 2017

Minglani, M., Diehl, J., Cao, X., Li, B., Park, D., Lilja, D. J., & Du, D. H. C. (2017, December). Kinetic Action: Performance Analysis of Integrated Key-Value Storage Devices vs. LevelDB Servers. 2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS). https://doi.org/10.1109/icpads.2017.00072

Education

University of Illinois Urbana-Champaign

Ph.D., Electrical Engineering

Urbana, Illinois, United States of America

University of Illinois Urbana-Champaign

M.S., Electrical Engineering

Urbana, Illinois, United States of America

Iowa State University

B.S., Computer Engineering

Ames, Iowa, United States of America

Experience

University of Minnesota - Twin Cities

Professor

Department Head

University of Canterbury, Christchurch, New Zealand

Visiting Professor

University of Western Australia, Perth, Australia

Visiting Professor

IBM, Rochester, Minnesota

Visiting Senior Engineer

Tandem Computers, Inc., Cupertino, CA

Development Engineer

Links & Social Media

Join David on NotedSource!
Join Now

At NotedSource, we believe that professors, post-docs, scientists and other researchers have deep, untapped knowledge and expertise that can be leveraged to drive innovation within companies. NotedSource is committed to bridging the gap between academia and industry by providing a platform for collaboration with industry and networking with other researchers.

For industry, NotedSource identifies the right academic experts in 24 hours to help organizations build and grow. With a platform of thousands of knowledgeable PhDs, scientists, and industry experts, NotedSource makes connecting and collaborating easy.

For academic researchers such as professors, post-docs, and Ph.D.s, NotedSource provides tools to discover and connect to your colleagues with messaging and news feeds, in addition to the opportunity to be paid for your collaboration with vetted partners.

Expert Institutions
NotedSource has experts from Stanford University
Expert institutions using NotedSource include Oxfort University
Experts from McGill have used NotedSource to share their expertise
University of Chicago experts have used NotedSource
MIT researchers have used NotedSource
Proudly trusted by
Microsoft uses NotedSource for academic partnerships
Johnson & Johnson academic research projects on NotedSource
ProQuest (Clarivate) uses NotedSource as their industry academia platform
Slamom consulting engages academics for research collaboration on NotedSource
Omnicom and OMG find academics on notedsource
Unilever research project have used NotedSource to engage academic experts